1. Field of the Invention
The present invention generally relates to a system and method for processing a High Definition Television (HDTV) image. More particularly, the present invention provides a plurality of encoders connected in parallel and directly attached to a HDTV video source for processing a HDTV image.
2. Background Art
The advent of the High Definition Television (HDTV) standard, and the requirement to perform Moving Pictures Experts Group (MPEG) video compression on images in the HDTV format, has created significant video data processing demands on MPEG-2 encoder Application Specific Integrated Circuits (ASICs). Specifically, encoders that compress video data in Standard Definition (SD) format typically process 480 active video lines (i.e., out of a total of 525 lines per video frame) consisting of 720 active luminance and chrominance pixels (i.e., out of a total of 858) at a 13.5 MHz pixel clock rate for an input rate of 30 frames per second. Conversely, a MPEG-2 encoder must typically process incoming HDTV pixel data (e.g., one luminance and one chrominance pixel data byte) 5-6 times faster to yield the same input rate of 30 frames per second. That is, 1080 or 1088 active video lines (i.e., out of a total of 1125 lines per video frame) consisting of 1920 active luminance and chrominance pixels (i.e., out of a total of 2200) per line are scanned into the encoder at a pixel clock rate of 74.25 MHz.
With present technology, it is generally not feasible to for a single MPEG-2 encoder to process/compress HDTV images at full resolution (i.e., 5-6 times faster than for Standard Definition). It is therefore necessary to have a HDTV MPEG-2 video architecture that utilizes multiple encoders to process a single HDTV image at fill resolution. With such an architecture, an image must be split horizontally or vertically into multiple portions for processing by the encoders. In splitting the HDTV image, problems arise in that a large amount of logic and memory, external to the encoders, is required. Specifically, external logic must be provided to buffer and split the HDTV image into smaller portions. The external logic would then send a particular portion of the HDTV image to each of the encoders.
An additional problem often encountered is that many encoders can accept pixel data only at the Standard Definition pixel clock rate of 13.5 MHz. As indicated above, the HDTV pixel clock rate is approximately 74.25 MHz. Thus, the external logic may be forced to accept data at 74.25 MHz, but transmit the data to the encoders at 13.5 MHz. Providing this capability adds more complexity to the external control logic as well as significantly more external memory buffers. Accordingly, the requirement for system designers to include external splitter and control logic (collectively referred to as glue logic) significantly drives up the overall system cost and complexity.
In view of the foregoing, there exists a need for a system and method for processing a HDTV image. In addition, there exists a need for a system and method for directly attaching a plurality of video encoders to a HDTV video source such that external splitter and control logic is not required. In addition, there exists a need for the encoders to be programmable so that each encoder receives an entire HDTV image from the HDTV video source, but processes only a portion thereof.